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Allwinner /D1H /TWI[2] /TWI_DRV_INT_CTRL

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Interpret as TWI_DRV_INT_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (tran_com_pd)tran_com_pd 0 (tran_err_pd)tran_err_pd 0 (tx_req_pd)tx_req_pd 0 (rx_req_pd)rx_req_pd 0 (tran_com_int_en)tran_com_int_en 0 (tran_err_int_en)tran_err_int_en 0 (tx_req_int_en)tx_req_int_en 0 (rx_req_int_en)rx_req_int_en

Description

TWI_DRV Interrupt Control Register

Fields

tran_com_pd
tran_err_pd
tx_req_pd
rx_req_pd
tran_com_int_en
tran_err_int_en
tx_req_int_en
rx_req_int_en

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data